Which of the following connects the L2 cache to the processor？（）
A: PCI
B: Frontside bus
C: Backside bus
D: System I/O bus
A: PCI
B: Frontside bus
C: Backside bus
D: System I/O bus
举一反三
- In Verilog HDL, which option is the correct interpretation of the following statement? assign bus [7:4] = {bus [0], bus [1], bus[2], bus[3] } ; A: bus[0], bus[1], bus[2] and bus[3] are assigned to bus[4], bus[5], bus[6] and bus[7] respectively B: bus[0], bus[1], bus[2] and bus[3] are assigned to bus[7], bus[6], bus[5] and bus[4] respectively C: The values of bus[0], bus[1], bus[2] and bus[3] remain unchanged D: All the values of bus[0], bus[1], bus[2] and bus[3] become binary 0
- This bus connects the CPU to memory on the system board.() A: HDMI B: USB C: system D: thunderbolt
- Which bus can I takeWhich bus ________________________
- 2. Which bus will the woman take? A: Bus number 4 B: Bus number 6 C: Bus number 2 D: ...
- Which of the following are primary differences between a laptop and a desktop CPU？（） A: heat production B: L2 Cache C: clock speed D: front side bus E: power consumption