Name the three types of bus which are used when external memory is connected to the 8051.( ) A: Address bus B: Control bus C: Data bus D: Enable bus

6. 计算机总线按照功能可分为？ A: 地址总线（Address Bus） B: 数据总线（Data Bus） C: 控制总线（Control Bus） D: 系统总线（System Bus）

_______ is the control and data processing center of the whole computer system. A: Memory B: Motherboard C: CPU D: Bus

What is the control bus pin of MCU extended data memory? A: ALE B: PSEN and ALE C: PSEN D: RD and WR

The width of address bus determines __________. A: word size B: maximum memory capacity of system C: carry data D: control signal

In Verilog HDL, which option is the correct interpretation of the following statement? assign bus [7:4] = {bus [0], bus [1], bus[2], bus[3] } ; A: bus[0], bus[1], bus[2] and bus[3] are assigned to bus[4], bus[5], bus[6] and bus[7] respectively B: bus[0], bus[1], bus[2] and bus[3] are assigned to bus[7], bus[6], bus[5] and bus[4] respectively C: The values of bus[0], bus[1], bus[2] and bus[3] remain unchanged D: All the values of bus[0], bus[1], bus[2] and bus[3] become binary 0

18.A) Bus 7.B) Bus 70.C) Bus 17.D) Bus 20. A: Bus 7. B: Bus 70. C: Bus 17. D: Bus 20.

Verilog HDL中，下面语句的正确解释是：（）assign bus [7:4] = {bus [0], bus [1], bus[2], bus[3] } ; A: bus[0]、bus[1]、bus[2]、bus[3]分别赋值给bus[4]、bus[5]、bus[6]、bus[7] B: bus[0]、bus[1]、bus[2]、bus[3]分别赋值给bus[7]、bus[6]、bus[5]、bus[4] C: bus[0]、bus[1]、bus[2]和bus[3]的值保持不变 D: bus[0]、bus[1]、bus[2]和bus[3]的值均变为二进制0

My cousin always _______ to school. A: by bus B: by a bus C: take a bus D: takes a bus

Be careful! ______ ! A: The bus comes here B: Here comes the bus C: The bus here is D: There is the bus