下面是一个4位的双向移位寄存器程序，该程序正确吗？module UniversalShift (S1,S0,Din,Dsl,Dsr,Q,CP,CLR_); input S1, S0; //Select inputs input Dsl, Dsr; //Serial Data inputs input CP, CLR_; //Clock and Reset input [3:0] Din; //Parallel Data input output [3:0] Q; //Register output reg [3:0] Q; always @ (posedge CP or negedge CLR_) if (~CLR_) Q <= 4b0000; else case ({S1,S0}) 2b00: Q <= Q; //No change 2b01: Q <= {Dsr,Q[3:1]}; //Shift right 2b10: Q <= {Q[2:0],Dsl}; //Shift left 2b11: Q <= Din; //Parallel load input endcaseendmodule

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2021-04-14

下面是一个4位的双向移位寄存器程序，该程序正确吗？module UniversalShift (S1,S0,Din,Dsl,Dsr,Q,CP,CLR_); input S1, S0; //Select inputs input Dsl, Dsr; //Serial Data inputs input CP, CLR_; //Clock and Reset input [3:0] Din; //Parallel Data input output [3:0] Q; //Register output reg [3:0] Q; always @ (posedge CP or negedge CLR_) if (~CLR_) Q <= 4b0000; else case ({S1,S0}) 2b00: Q <= Q; //No change 2b01: Q <= {Dsr,Q[3:1]}; //Shift right 2b10: Q <= {Q[2:0],Dsl}; //Shift left 2b11: Q <= Din; //Parallel load input endcaseendmodule

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