下列哪一个表述是正确: A: always@(posedge CLK or RST) B: always@(posedge CLK or negedge RST or A) C: always@(posedge CLK or D or Q) D: always@(posedge CLK or negedge RST)
下列哪一个表述是正确: A: always@(posedge CLK or RST) B: always@(posedge CLK or negedge RST or A) C: always@(posedge CLK or D or Q) D: always@(posedge CLK or negedge RST)
下列哪一个表述是正确: A: always@(posedge CLK or RST) B: always@(posedge CLK or negedge RST or A) C: always@(posedge CLK or D or Q) D: always@(posedge CLK or negedge RST)
下列哪一个表述是正确: A: always@(posedge CLK or RST) B: always@(posedge CLK or negedge RST or A) C: always@(posedge CLK or D or Q) D: always@(posedge CLK or negedge RST)
下列Verilog HDL代码描述中,采用时钟信号clock上升沿和复位信号reset下降沿触发的是( )。 A: always @ ( posedge clock, negedge reset ) if ( reset ) B: always @ ( posedge clock, negedge reset ) if ( ! reset ) C: always @ ( clock, reset ) if ( reset ) D: always @ ( posedge clock or negedge reset ) if ( reset==0 )
下列Verilog HDL代码描述中,采用时钟信号clock上升沿和复位信号reset下降沿触发的是( )。 A: always @ ( posedge clock, negedge reset ) if ( reset ) B: always @ ( posedge clock, negedge reset ) if ( ! reset ) C: always @ ( clock, reset ) if ( reset ) D: always @ ( posedge clock or negedge reset ) if ( reset==0 )
时钟上升沿敏感的关键词是: A: always B: module C: posedge D: negedge
时钟上升沿敏感的关键词是: A: always B: module C: posedge D: negedge
时钟上升沿敏感的关键词是: A: always B: module C: posedge D: negedge
时钟上升沿敏感的关键词是: A: always B: module C: posedge D: negedge
用Verilog HDL设计用时钟clk的下降沿触发的同步计数器时,在always语句的敏感参数表中,必须包含有( )参数。 A: clk B: posedge clk C: negedge clk D: negedge clk
用Verilog HDL设计用时钟clk的下降沿触发的同步计数器时,在always语句的敏感参数表中,必须包含有( )参数。 A: clk B: posedge clk C: negedge clk D: negedge clk
在基于Verilog HDL的触发器的设计中,能够实现下降沿触发的关键字是( )。 A: posedge B: negedge C: notif0 D: notif1
在基于Verilog HDL的触发器的设计中,能够实现下降沿触发的关键字是( )。 A: posedge B: negedge C: notif0 D: notif1
系统建模时,避免使用的语句 。 A: 与X、Z的比较 B: 延时 C: 敏感列表里同时带有posedge和negedge D: primitives
系统建模时,避免使用的语句 。 A: 与X、Z的比较 B: 延时 C: 敏感列表里同时带有posedge和negedge D: primitives
下列Moore型状态机采用Verilog语言主控时序部分正确的是: A: always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end B: always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end C: always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state; D: always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;
下列Moore型状态机采用Verilog语言主控时序部分正确的是: A: always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end B: always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end C: always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state; D: always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;
下列Moore型状态机采用Verilog语言主控时序部分正确的是: A: always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end B: always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end C: always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state; D: always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;
下列Moore型状态机采用Verilog语言主控时序部分正确的是: A: always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end B: always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end C: always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state; D: always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;