• 2022-10-25
    正常情况下,AC BUS1给AC ESS BUS供电,当AC BUS1失效时,AC ESS BUS可以由( )供电
    A: EMER GEN
    B: ESS SHED BUS
    C: AC BUS2
  • C

    举一反三

    内容

    • 0

      正常情况下,IES由谁提供主输入电源?() A: DC BUS 1 B: DC BUS 2 C: DC ESS BUS 1 D: DC ESS BUS 2

    • 1

      如果TR1和TR2失效,以下说法哪种正确() A: ADC BUS 1,DC BUS 2和DC BAT BUS同时失效 B: BDC ESS BUS由ESS TR供电 C: C以上都对

    • 2

      Verilog HDL中,下面语句的正确解释是:()assign bus [7:4] = {bus [0], bus [1], bus[2], bus[3] } ; A: bus[0]、bus[1]、bus[2]、bus[3]分别赋值给bus[4]、bus[5]、bus[6]、bus[7] B: bus[0]、bus[1]、bus[2]、bus[3]分别赋值给bus[7]、bus[6]、bus[5]、bus[4] C: bus[0]、bus[1]、bus[2]和bus[3]的值保持不变 D: bus[0]、bus[1]、bus[2]和bus[3]的值均变为二进制0

    • 3

      In Verilog HDL, which option is the correct interpretation of the following statement? assign bus [7:4] = {bus [0], bus [1], bus[2], bus[3] } ; A: bus[0], bus[1], bus[2] and bus[3] are assigned to bus[4], bus[5], bus[6] and bus[7] respectively B: bus[0], bus[1], bus[2] and bus[3] are assigned to bus[7], bus[6], bus[5] and bus[4] respectively C: The values of bus[0], bus[1], bus[2] and bus[3] remain unchanged D: All the values of bus[0], bus[1], bus[2] and bus[3] become binary 0

    • 4

      18.A) Bus 7.B) Bus 70.C) Bus 17.D) Bus 20. A: Bus 7. B: Bus 70. C: Bus 17. D: Bus 20.