下列Verilog HDL程序所描述电路是（ ）module TRI (EN, IN, OUT);input IN, EN;output OUT;assign OUT = EN ? IN : 1bZ;endmodule
举一反三
- 下列Verilog HDL程序所描述电路是（）module ...? IN : 1bZ;endmodule
- 下面哪种代码执行后是与其他结果不一样的？ A: module mux2_1(a,b,sel,out); input a,b,sel; output out; assign out=(sel==1)?a:b; endmodule B: module mux2_1(a,b,sel,out); input a,b,sel; output out; reg out; always@(a or b or sel) begin case(sel) 0: out=a; 1: out=b; endcase end endmodule C: module mux2_1(a,b,sel,out); input a,b,sel; output out; reg out; always@(*) if(sel==0) out=a; else out=b; endmodule
- 下列Verilog HDL程序所描述电路功能是（）modul... & A[0] );endmodule
- MOV指令是方框指令，使能输入是EN,使能输出是ENO,输入端是EN，输出端是OUT（）
- 下列Verilog HDL程序所描述电路功能是 .module _4bit_cnt (CP,nCR,Q,Mod); input CP, nCR, Mod; output reg [3:0] Q; always @ (posedge CP or negedge nCR) if (~nCR) Q <= 4b0000; else if (Mod==1) Q <= Q + 1b1; elseQ <= Q - 1b1; endmodule