下面哪种代码执行后是与其他结果不一样的？ A: module mux2_1(a,b,sel,out); input a,b,sel; output out; assign out=(sel==1)?a:b; endmodule B: module mux2_1(a,b,sel,out); input a,b,sel; output out; reg out; always@(a or b or sel) begin case(sel) 0: out=a; 1: out=b; endcase end endmodule C: module mux2_1(a,b,sel,out); input a,b,sel; output out; reg out; always@(*) if(sel==0) out=a; else out=b; endmodule

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2022-06-08

下面哪种代码执行后是与其他结果不一样的？ A: module mux2_1(a,b,sel,out); input a,b,sel; output out; assign out=(sel==1)?a:b; endmodule B: module mux2_1(a,b,sel,out); input a,b,sel; output out; reg out; always@(a or b or sel) begin case(sel) 0: out=a; 1: out=b; endcase end endmodule C: module mux2_1(a,b,sel,out); input a,b,sel; output out; reg out; always@(*) if(sel==0) out=a; else out=b; endmodule

下面哪种代码执行后是与其他结果不一样的？
A: module mux2_1(a,b,sel,out); input a,b,sel; output out; assign out=(sel==1)?a:b; endmodule
B: module mux2_1(a,b,sel,out); input a,b,sel; output out; reg out; always@(a or b or sel) begin case(sel) 0: out=a; 1: out=b; endcase end endmodule
C: module mux2_1(a,b,sel,out); input a,b,sel; output out; reg out; always@(*) if(sel==0) out=a; else out=b; endmodule

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