下列敏感信号的表示属于边沿敏感型的是________
A: always@(posedge clk or posedge clr)
B: always@(A or B)
C: always@(posedge clk or clr)
D: always @ (*)
A: always@(posedge clk or posedge clr)
B: always@(A or B)
C: always@(posedge clk or clr)
D: always @ (*)
举一反三
- 下列哪一个表述是正确： A: always@(posedge CLK or RST) B: always@(posedge CLK or negedge RST or A) C: always@(posedge CLK or D or Q) D: always@(posedge CLK or negedge RST)
- 下列哪一个表述是正确： A: always@(posedge CLK or RST) B: always@(posedge CLK or negedge RST or A) C: always@(posedge CLK or D or Q) D: always@(posedge CLK or negedge RST)
- 下列Moore型状态机采用Verilog语言主控时序部分正确的是： A: always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end B: always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end C: always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state; D: always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;
- 下列过程语句always的敏感信号列表语法有问题的是() A: always@(aorb) B: always@(posedgeclk) C: always@* D: always@(posedgeclkorclr)
- 异步时序电路module AMOD(D,A,CLK,Q); output Q; input A,D,CLK; reg Q,Q1; always @(posedge CLK)Q1 <= ~(A | Q); always @(posedge ____ )Q <= D;endmodule空格处应该填入： A: CLK B: Q1 C: D D: A