下列标识符表述错误的是 A: shiftreg_a B: n$657 C: 112233 D: _bus3
下列标识符表述错误的是 A: shiftreg_a B: n$657 C: 112233 D: _bus3
下列Verilog HDL程序所描述电路功能是（ ）module ShiftReg (Q,Din,CP,CLR_); input Din; //Serial Data inputs input CP, CLR_; //Clock and Reset output reg [3:0] Q; //Register output always @ (posedge CP or negedge CLR_) if (!CLR_) Q <= 4b0000; else begin //Shift right Q[0] <= Din; Q[3:1] <= Q[2:0]; endendmodule
下列Verilog HDL程序所描述电路功能是（ ）module ShiftReg (Q,Din,CP,CLR_); input Din; //Serial Data inputs input CP, CLR_; //Clock and Reset output reg [3:0] Q; //Register output always @ (posedge CP or negedge CLR_) if (!CLR_) Q <= 4b0000; else begin //Shift right Q[0] <= Din; Q[3:1] <= Q[2:0]; endendmodule
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