执行下列语句后，结果是
always@(posedgeclk)
begin
b<=a;
c<=b;
end
always@(posedgeclk)
begin
b<=a;
c<=b;
end
举一反三
- 执行下列语句后，结果是 always @(posedge clk) begin b <= a ; c <= b; end
- 下列过程语句always的敏感信号列表语法有问题的是() A: always@(aorb) B: always@(posedgeclk) C: always@* D: always@(posedgeclkorclr)
- 下列Moore型状态机采用Verilog语言主控时序部分正确的是： A: always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end B: always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end C: always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state; D: always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;
- 以下程序中，clk_50M为50MHz输入时钟，若想输出clk为2Hz的方波，则cnt的判断条件设置为多少？（） always@(posedge clk_50M) begin if (cnt == ? ) begin clk2_hz = 1'b1; cnt = 0; end else begin cnt = cnt + 1; clk2_hz = 1'b0; end end always@(posedge clk2_hz) clk =~ clk;
- 在VerilogHDL中，语句“always@（posedgeclk）”表示模块的事件是由clk的（）触发的。 A: 下降沿 B: 上升沿 C: 高电平 D: 低电平