执行下列语句后，结果是 always @(posedge clk) begin b <= a ; c <= b; end
举一反三
- 执行下列语句后，结果是 always@(posedgeclk) begin b<=a; c<=b; end
- 下面为某可变计数器的Verilog HDL代码，当A=1时，为7进制；当A=0时，为9进制。试补充完空白处代码。 module Alterable_Counter(A, clk, Q); input clk, A; output reg [3:0] Q; parameter N=7; parameter M=9; always @(posedge clk) begin if(A) begin if (__________) begin Q<=0; end else begin Q<=_______; end end else begin if (___________) begin Q<=0; end else begin Q<=Q+1; end end end endmodule
- 下列Moore型状态机采用Verilog语言主控时序部分正确的是： A: always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end B: always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end C: always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state; D: always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;
- 以下程序中，clk_50M为50MHz输入时钟，若想输出clk为2Hz的方波，则cnt的判断条件设置为多少？（） always@(posedge clk_50M) begin if (cnt == ? ) begin clk2_hz = 1'b1; cnt = 0; end else begin cnt = cnt + 1; clk2_hz = 1'b0; end end always@(posedge clk2_hz) clk =~ clk;
- 下列敏感信号的表示属于边沿敏感型的是________ A: always@(posedge clk or posedge clr) B: always@(A or B) C: always@(posedge clk or clr) D: always @ (*)