阅读下列两个程序,画出它们的逻辑图。module DFFI (Qa,Qb,D,CP); input D,CP; output reg Qa,Qb; always @ ( posedge CP) begin Qa= D; Qb= Qa; end endmodule
阅读下列两个程序,画出它们的逻辑图。module DFFI (Qa,Qb,D,CP); input D,CP; output reg Qa,Qb; always @ ( posedge CP) begin Qa= D; Qb= Qa; end endmodule
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