下列Verilog HDL程序所描述电路功能是 .module _4bit_cnt (CP,nCR,Q,Mod); input CP, nCR, Mod; output reg [3:0] Q; always @ (posedge CP or negedge nCR) if (~nCR) Q <= 4b0000; else if (Mod==1) Q <= Q + 1b1; elseQ <= Q - 1b1; endmodule
下列Verilog HDL程序所描述电路功能是 .module _4bit_cnt (CP,nCR,Q,Mod); input CP, nCR, Mod; output reg [3:0] Q; always @ (posedge CP or negedge nCR) if (~nCR) Q <= 4b0000; else if (Mod==1) Q <= Q + 1b1; elseQ <= Q - 1b1; endmodule
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