定义状态机当前状态为state ,次态为next _state; 输入a,输出b, 则下列为Mealy状态机的写法是：
A: always@（posedge clk）case (state )0:next_state<=1;1:next_state<=x;
B: always@（posedge clk）case (state )0: if（a==0）next_state<=1; else next_state<=x;1:next_state<=x;
C: always@（posedge clk）case (state )0: if（state==0）next_state<=1; else next_state<=x;1:next_state<=x;
D: 以上都是正确的
A: always@（posedge clk）case (state )0:next_state<=1;1:next_state<=x;
B: always@（posedge clk）case (state )0: if（a==0）next_state<=1; else next_state<=x;1:next_state<=x;
C: always@（posedge clk）case (state )0: if（state==0）next_state<=1; else next_state<=x;1:next_state<=x;
D: 以上都是正确的
举一反三
- 以下的描述中，必然是对Mealy型状态机的描述的是？ A: always@(*)case(state)S0:beginout=0;if(in)next_state=S1;elsenext_state=S2;end…… B: always@(*)case(state)S0:beginif(in)next_state=S1;elsenext_state=S0;end…… C: always@(*)case(state)S0:beginif(in)beginnext_state=S1;out=1endelsenext_state=S0;end…… D: 以上答案均不正确
- 定义状态机当前状态为state,次态为next_state;输入a,输出b,则下列为Mealy状态机的写法是：
- 下列Moore型状态机采用Verilog语言主控时序部分正确的是： A: always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end B: always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end C: always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state; D: always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;
- 下列Moore型状态机采用Verilog语言主控时序部分正确的是： A: always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end B: always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end C: always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state; D: always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;
- The output of a Mealy machine depends on its A: inputs B: present state C: next state D: answers (a) and (c)