定义状态机当前状态为state ,次态为next _state; 输入a,输出b, 则下列为Mealy状态机的写法是： A: always@（posedge clk）case (state )0:next_state<=1;1:next_state<=x; B: always@（posedge clk）case (state )0: if（a==0）next_state<=1; else next_state<=x;1:next_state<=x; C: always@（posedge clk）case (state )0: if（state==0）next_state<=1; else next_state<=x;1:next_state<=x; D: 以上都是正确的

以下的描述中，必然是对Mealy型状态机的描述的是？ A: always@(*)case(state)S0:beginout=0;if(in)next_state=S1;elsenext_state=S2;end…… B: always@(*)case(state)S0:beginif(in)next_state=S1;elsenext_state=S0;end…… C: always@(*)case(state)S0:beginif(in)beginnext_state=S1;out=1endelsenext_state=S0;end…… D: 以上答案均不正确

定义状态机当前状态为state,次态为next_state;输入a,输出b,则下列为Mealy状态机的写法是：

The output of a Mealy machine depends on its A: inputs B: present state C: next state D: answers (a) and (c)

下述程序中能够实现安全状态机设计的是： A: Parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7;...s5: next_state =s0;S6: next_state =s0;S7: next_state =s0;default:begin next_state =s0; B: `define s0=1,s1=2,s2=4,s3=4,s4=8s5: next_state =s1;S6: next_state =s1;S7: next_state =s2;default:begin next_state =s0; C: Parameter s0=40,s1=41,s2=42,s3=43,s4=44,s5=45,s6=46,s7=47;...s5: next_state =s0;S6: next_state =s0;S7: next_state =s0; D: 以上都正确

下述程序中能够实现安全状态机设计的是 A: Parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7;...s5: next_state =s0;S6: next_state =s0;S7: next_state =s0;default:begin next_state =s0; B: define s0=1,s1=2,s2=4,s3=4,s4=8s5: next_state =s1;S6: next_state =s1;S7: next_state =s2;default:begin next_state =s0; C: Parameter s0=40,s1=41,s2=42,s3=43,s4=44,s5=45,s6=46,s7=47;...s5: next_state =s0;S6: next_state =s0;S7: next_state =s0; D: 以上都是正确选型

下列Moore型状态机采用Verilog语言主控时序部分正确的是： A: always@(posedge clk or negedge reset) begin if(!reset) current_state&lt;=s0; else current_state&lt;=next_state; end B: always@(posedge clk ) begin if(!reset) current_state&lt;=s0; else current_state&lt;=next_state; end C: always@(posedge clk t) if(reset) current_state&lt;=s0; else current_state&lt;=next_state; D: always@(posedge clk or negedge reset) if(reset) current_state&lt;=s0; else current_state&lt;=next_state;

下列Moore型状态机采用Verilog语言主控时序部分正确的是： A: always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end B: always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end C: always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state; D: always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;

下列Moore型状态机采用Verilog语言说明部分正确的是： A: parameter [2:0] s0=0, s1=1,s2=2,s3=3,s4=4;reg [2:0] current_state, next_state; B: parameter [1:0] s0=0, s1=1,s2=2,s3=3,s4=4;reg [1:0] current_state, next_state; C: TYPE FSM_ST IS (s0, s1,s2,s3,s4); SIGNAL current_state, next_state: FSM_ST; D: typedef enum {s0, s1,s2,s3,s4} type_user;type_user current_state, next_state

6. contact A: the state of talking or speaking B: the state of acting C: the state of communicating or meeting D: the state of laughing